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پایان نامه و تز
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این مجموعه بیش از 180 پایان نامه و تز در مورد  مبدل آنالوگ به دیجیتال  است .

این مجموعه آخرین پایان نامه های کار شده تا سال 2011 است.

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Analog to Digital Converter 

را مشاهده کنید.
1.
Adaptive blocker rejection continuous-time sigma-delta ADC
by Kim, Hyung Seok, Ph.D., Arizona State University, 2010, 133 pages; AAT 3407142
› 58 references
Preview (548 K) ***  Full Text - PDF (4 MB)
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2.
A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS
by Sarvari, Siamak, M.A.Sc., University of Toronto (Canada), 2010, 90 pages; AAT MR76232
 Abstract
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3.
A 400 MHz SigmaDelta ADC for band-pass if digitization around 100 MHz with excess loop delay compensation
by Gupta, Akhil, M.S., The George Washington University, 2010, 86 pages; AAT 1482914
› 29 references
Preview (1 MB) ***  Full Text - PDF (4 MB)
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4.
Analog Front-End Design for 2x Blind ADC-based Receivers
by Tahmoureszadeh, Tina, M.A.Sc., University of Toronto (Canada), 2010, 86 pages; AAT MR76216
 Abstract
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5.
High Speed ADC Design Methodology
by Tang, He, Ph.D., University of California, Riverside, 2010, 148 pages; AAT 3433899
› 45 references
Preview (559 K) ***  Full Text - PDF (4 MB)
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6.
Low-power high-performance SAR ADC design with digital calibration techniques
by Liu, Wenbo, Ph.D., University of Illinois at Urbana-Champaign, 2010, 153 pages; AAT 3455823
 Abstract
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7.
A 7-bit 2.5GS/sec time-interleaved C-2C SAR ADC for 60GHz multi-band OFDM-based receivers
by Alpman, Erkan, Ph.D., Carnegie Mellon University, 2009, 204 pages; AAT 3376477
› 98 references
Preview (309 K) ***  Full Text - PDF (3 MB)
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8.
A 10-bit 500-MHz 55-mW CMOS ADC
by Verma, Ashutosh, Ph.D., University of California, Los Angeles, 2009, 109 pages; AAT 3364119
› 38 references
Preview (681 K) ***  Full Text - PDF (4 MB)
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9.
A frequency-scalable 14-bit ADC for low power sensor applications
by Liang, Joshua, M.A.Sc., University of Toronto (Canada), 2009, 141 pages; AAT MR59248
› 34 references
Preview (482 K) ***  Full Text - PDF (3 MB)
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10.
Design of a wideband low-power continuous-time sigma-delta (SigmaDelta) analog-to-digital converter (ADC) in 90nm CMOS technology
by Chen, Fang, Ph.D., University of Windsor (Canada), 2009, 149 pages; AAT NR57568
› 75 references
Preview (338 K) ***  Full Text - PDF (3 MB)
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11.
A closed-loop Deep Brain Stimulation device with a logarithmic pipeline ADC
by Lee, Jongwoo, Ph.D., University of Michigan, 2008, 138 pages; AAT 3328877
Preview (1 MB) ***  Full Text - PDF (7 MB)
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12.
A single-channel 10b 1GS/s ADC with 2-cycle latency using pipelined cascaded folding architecture
by Razzaghi, Alireza, Ph.D., University of California, Los Angeles, 2008, 255 pages; AAT 3316981
› 85 references
Preview (270 K) ***  Full Text - PDF (3 MB)
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13.
A 1V 2.5GS/s 8-bit self-calibrated flash ADC in 90nm GP CMOS
by Yu, Hairong, Ph.D., University of California, Los Angeles, 2008, 167 pages; AAT 3322043
› 46 references
Preview (201 K) ***  Full Text - PDF (2 MB)
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14.
Calibration of multi-bit per stage pipelined ADC using statistical properties of capacitor arrays
by Ray, Sourja, Ph.D., University of California, San Diego, 2008, 171 pages; AAT 3313483
› 113 references
Preview (524 K) ***  Full Text - PDF (5 MB)
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15.
Nested digital background calibration of a 12-bit pipelined ADC without an input SHA
by Wang, Haoyue, Ph.D., University of California, Davis, 2008, 107 pages; AAT 3350804
› 46 references
Preview (281 K) ***  Full Text - PDF (1 MB)
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16.
Pipelined ADC enhancement techniques
by Ahmed, S. Imran, Ph.D., University of Toronto (Canada), 2008, 203 pages; AAT NR44714
› 80 references
Preview (356 K) ***  Full Text - PDF (3 MB)
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17.
A dual-path 2-0 MASH ADC with dual digital error correction
by Zhang, Zhenyong, Ph.D., Oregon State University, 2007, 93 pages; AAT 3268271
Preview (285 K) ***  Full Text - PDF (3 MB)
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18.
High speed ADC design techniques
by Fan, Siqiang, Ph.D., Illinois Institute of Technology, 2007, 110 pages; AAT 3305327
Preview (612 K) ***  Full Text - PDF (4 MB)
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19.
Low-power sampled-data dual-slope ADC
by Malachira, Bopanna Kariappa, M.S.E.E., The University of Texas at Dallas, 2007, 65 pages; AAT 1448833
Preview (56 K) ***  Full Text - PDF (575 K)
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20.
A multipass spatial and temporal image filtering APS CMOS image sensor with pixel level ADC
by Chow, Jon, M.S., Tufts University, 2006, 118 pages; AAT 1437719
Preview (229 K) ***  Full Text - PDF (2 MB)
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21.
Design and realization of a single stage sigma-delta ADC with low oversampling ratio
by Cheng, Yongjie, Ph.D., Brigham Young University, 2006, 138 pages; AAT 3234396
Preview (445 K) ***  Full Text - PDF (4 MB)
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22.
Programmable application-specific ADC for digitally controlled switch-mode power supplies
by Parayandeh, Amir, M.A.Sc., University of Toronto (Canada), 2006, 96 pages; AAT MR21136
Preview (686 K) ***  Full Text - PDF (4 MB)
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23.
Accuracy enhancement techniques in low-voltage high-speed pipelined ADC design
by Li, Jipeng, Ph.D., Oregon State University, 2004, 120 pages; AAT 3115471
Preview (517 K) ***  Full Text - PDF (4 MB)
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24.
A low-voltage low-power 10-bit pipeline ADC in 90nm digital CMOS technology
by Wang, Robert, M.A.Sc., University of Toronto (Canada), 2004, 55 pages; AAT MQ95371
Preview (264 K) ***  Full Text - PDF (2 MB)
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25.
A 600 mega-sample/sec 8-bit ADC in 0.18mum CMOS
by Wang, Zhengyu, Ph.D., University of California, Los Angeles, 2004, 89 pages; AAT 3142564
Preview (444 K) ***  Full Text - PDF (3 MB)
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26.
A power scaleable and low power pipeline ADC using power resettable opamps
by Ahmed, Syed Imran, M.A.Sc., University of Toronto (Canada), 2004, 135 pages; AAT MQ95330
Preview (1 MB) ***  Full Text - PDF (8 MB)
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27.
Design of a wideband quadrature continuous-time delta-sigma ADC
by Yaghini, Navid, M.A.Sc., University of Toronto (Canada), 2004, 84 pages; AAT MQ95375
Preview (714 K) ***  Full Text - PDF (4 MB)
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28.
Partial analog equalization and ADC requirements in wired communications
by Hadji-Abdolhamid, Amir, Ph.D., University of Toronto (Canada), 2004, 156 pages; AAT NQ94311
Preview (940 K) ***  Full Text - PDF (7 MB)
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29.
Design methodology for mixed-signal AC BIST and ADC self-calibration
by Provost, Benoit, Ph.D., Texas A&M University, 2002, 209 pages; AAT 3050658
Preview (626 K) ***  Full Text - PDF (7 MB)
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30.
A re-configurable pipeline ADC architecture with built-in self-test techniques
by Liu, Hui, Ph.D., Iowa State University, 2001, 119 pages; AAT 3034203
Preview (623 K) ***  Full Text - PDF (3 MB)
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31.
Adaptive noise shaping in oversampled ADC based on LMS algorithm
by Koh, Jin-Seok, Ph.D., Texas A&M University, 2000, 141 pages; AAT 9994275
Preview (483 K) ***  Full Text - PDF (4 MB)
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32.
An 8b 80MS/s pipelined ADC with background calibration
by Ming, Jun, Ph.D., University of California, Davis, 2000, 123 pages; AAT 9980528
Preview (500 K) ***  Full Text - PDF (4 MB)
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33.
High-resolution high-bandwidth Sigma-Delta ADC in the transferred-substrate HBT technology
by Jaganathan, Shrinivasan, Ph.D., University of California, Santa Barbara, 2000, 161 pages; AAT 3013217
Preview (510 K) ***  Full Text - PDF (5 MB)
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34.
Analysis of manufacturability factors for analog CMOS ADC building blocks
by Ockey, Rachelle Deanne, M.A.Sc., Simon Fraser University (Canada), 1999, 101 pages; AAT MQ51437
Preview (579 K) ***  Full Text - PDF (4 MB)
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35.
Parallel Delta-Sigma ADC architectures
by Kong, Shyang Kye, Ph.D., University of California, San Diego, 1999, 162 pages; AAT 9938291
Preview (396 K) ***  Full Text - PDF (4 MB)
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36.
Initiation, development and implementation of Automatic Data Capture (ADC) technology in the broadcast system industry
by Klosterman, Jack, Jr., M.S., Northern Kentucky University, 1998, 61 pages; AAT EP25629
Preview (225 K) ***  Full Text - PDF (2 MB)
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37.
Modeling of In(0.49)Ga(0.51)P/GaAs heterojunction bipolar transistors for ADC and MMIC circuit design
by Barlage, Douglas William, Ph.D., University of Illinois at Urbana-Champaign, 1997, 133 pages; AAT 9812526
Preview (761 K) ***  Full Text - PDF (5 MB)
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