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پایان نامه و تز
پایان نامه و تز
.::فروش پایان نامه و تز لاتین::.

این مجموعه بیش از 800 پایان نامه و تز در مورد  VLSI  است .

این مجموعه آخرین پایان نامه های کار شده تا سال 2011 است.

برای خرید این مجموعه بصورت تکی یا کلی به قیمتی مناسب و گرفتن اطلاعات بیشتر با من تماس بگیرید.

در ادامه میتوانید عنوان پایان نامه ها و تزهای کار شده در زمینه

VLSI 

را مشاهده کنید.
201.
On-chip signaling techniques for nanometer VLSI designs
by Kaul, Himanshu, Ph.D., University of Michigan, 2005, 182 pages; AAT 3163839
Preview (781 K) ***  Full Text - PDF (8 MB)  
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202.
Performance and power dissipation optimizations for high-speed VLSI interconnect designs
by Li, Ruiming, Ph.D., The University of Texas at Dallas, 2005, 146 pages; AAT 3224355
Preview (2 MB) ***  Full Text - PDF (2 MB)  
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203.
Performance driven optimization of VLSI layout
by Choi, Wonjoon, Ph.D., University of Minnesota, 2005, 82 pages; AAT 3192010
Preview (421 K) ***  Full Text - PDF (3 MB)  
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204.
Physical planning of VLSI layout
by Yao, Bo, Ph.D., University of California, San Diego, 2005, 93 pages; AAT 3189794
Preview (612 K) ***  Full Text - PDF (4 MB)  
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205.
Probabilistic interval-valued computation: Representing and reasoning about uncertainty in DSP and VLSI design
by Fang, Claire Fang, Ph.D., Carnegie Mellon University, 2005, 182 pages; AAT 3171943
Preview (678 K) ***  Full Text - PDF (8 MB)  
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206.
Process development and characterization of via structures in silicon for three-dimensional VLSI systems
by Spiesshoefer, Silke, Ph.D., University of Arkansas, 2005, 176 pages; AAT 3207129
Preview (611 K) ***  Full Text - PDF (10 MB)  
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207.
Process variation aware high performance low power VLSI system design in nano-scale regime
by Agarwal, Amit, Ph.D., Purdue University, 2005, 166 pages; AAT 3198152
Preview (288 K) ***  Full Text - PDF (5 MB)  
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208.
Routing algorithms for high-performance VLSI packaging
by Ozdal, Muhammet Mustafa, Ph.D., University of Illinois at Urbana-Champaign, 2005, 152 pages; AAT 3199107
Preview (841 K) ***  Full Text - PDF (7 MB)  
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209.
Scalable partitioning-driven algorithms for solving complex and emerging problems in VLSI physical design automation
by Selvakkumaran, Navaratnasothie, Ph.D., University of Minnesota, 2005, 129 pages; AAT 3172843
Preview (682 K) ***  Full Text - PDF (6 MB)  
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210.
Sequential/parallel heuristic algorithms for VLSI standard cell placement
by Lu, Guangfa, M.Sc., University of Guelph (Canada), 2005, 161 pages; AAT MR01830
Preview (540 K) ***  Full Text - PDF (6 MB)  
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211.
Sleepy stack: A new approach to low power VLSI logic and memory
by Park, Jun Cheol, Ph.D., Georgia Institute of Technology, 2005, 170 pages; AAT 3183245
Preview (106 K) ***  Full Text - PDF (2 MB)  
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212.
SPICE-accurate iterative methods for efficient time-domain simulation of VLSI circuits with strong parasitic couplings
by Li, Zhao, Ph.D., University of Washington, 2005, 107 pages; AAT 3163395
Preview (614 K) ***  Full Text - PDF (4 MB)  
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213.
Static learning for problems in VLSI test and verification
by Syal, Manan, Ph.D., Virginia Polytechnic Institute and State University, 2005, 129 pages; AAT 3255406
Preview (122 K) ***  Full Text - PDF (583 K)  
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214.
System architectures and VLSI implementations of secure embedded systems
by Hwang, David Delchi, Ph.D., University of California, Los Angeles, 2005, 181 pages; AAT 3175189
Preview (486 K) ***  Full Text - PDF (7 MB)  
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215.
Timing analysis of CMOS logic gates in deep submicron VLSI design
by Jiang, Xueping, Ph.D., Colorado State University, 2005, 327 pages; AAT 3173032
Preview (1 MB) ***  Full Text - PDF (11 MB)  
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216.
Timing optimization for nano-meter VLSI designs
by Yeh, Chao-Yang (Steve), Ph.D., University of California, Santa Barbara, 2005, 140 pages; AAT 3186808
Preview (191 K) ***  Full Text - PDF (1 MB)  
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217.
VLSI architecture for a dual base multiplier
by Cheemala, Jessy Marinasagar, M.S., Texas A&M University - Kingsville, 2005, 97 pages; AAT 1427307
Preview (1 MB) ***  Full Text - PDF (6 MB)  
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218.
VLSI architectures for high-speed transceivers
by Gu, Yongru, Ph.D., University of Minnesota, 2005, 160 pages; AAT 3179990
Preview (973 K) ***  Full Text - PDF (10 MB)  
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219.
VLSI design optimization for lifting scheme DWT
by Li, Jian, M.S., Michigan State University, 2005, 70 pages; AAT 1428951
Preview (404 K) ***  Full Text - PDF (2 MB)  
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220.
VLSI implementation of steerable spatiotemporal filters for focal-plane adaptive image processing
by Gruev, Viktor, Ph.D., The Johns Hopkins University, 2005, 207 pages; AAT 3155620
Preview (912 K) ***  Full Text - PDF (8 MB)  
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221.
A high-frequency, soft-switching DC-DC converter for dynamic voltage scaling in VLSI loads
by Trescases, Olivier, M.A.Sc., University of Toronto (Canada), 2004, 116 pages; AAT MQ95368
Preview (687 K) ***  Full Text - PDF (5 MB)  
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222.
A highly scalable, parallel genetic algorithm for standard cell placement in VLSI design
by Zha, Zhenyu, D.E., Lamar University - Beaumont, 2004, 124 pages; AAT 3147979
Preview (593 K) ***  Full Text - PDF (3 MB)  
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223.
A memetic algorithm implementation on a FPGA for VLSI circuit partitioning
by Coe, Stephen, M.Sc., University of Guelph (Canada), 2004, 211 pages; AAT MQ96147
Preview (500 K) ***  Full Text - PDF (9 MB)  
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224.
A VLSI architecture for real-time matrix inversion
by Palli, Sudha, M.S., Texas A&M University - Kingsville, 2004, 77 pages; AAT 1423514
Preview (299 K) ***  Full Text - PDF (2 MB)  
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225.
A VLSI design paradigm for iterative decoders
by Elassal, Mahmoud, Ph.D., University of Louisiana at Lafayette, 2004, 120 pages; AAT 3153724
Preview (611 K) ***  Full Text - PDF (4 MB)  
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226.
A VLSI implementation of an adaptation algorithm for a pre-emphasis in a backplane transceiver
by Lin, Lei, M.A.Sc., Carleton University (Canada), 2004, 102 pages; AAT MQ89850
Preview (1 MB) ***  Full Text - PDF (9 MB)  
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227.
Behavioral and RT-level estimation and optimization of crosstalk in VLSI ASICs
by Gupta, Suvodeep, Ph.D., University of South Florida, 2004, 132 pages; AAT 3157212
Preview (168 K) ***  Full Text - PDF (675 K)  
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228.
Design and VLSI implementation of perceptive controller for robotic systems
by Sun, Yu, Ph.D., Michigan State University, 2004, 125 pages; AAT 3159010
Preview (837 K) ***  Full Text - PDF (4 MB)  
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229.
Design automation for physical synthesis of VLSI circuits and FPGAs
by Ababei, Cristinel, Ph.D., University of Minnesota, 2004, 128 pages; AAT 3154022
Preview (611 K) ***  Full Text - PDF (4 MB)  
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230.
Design of high performance, low power VLSI circuits for scaled technologies
by Kim, Hyung-il, Ph.D., Purdue University, 2004, 140 pages; AAT 3154657
Preview (833 K) ***  Full Text - PDF (11 MB)  
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231.
Electrothermal analysis of VLSI interconnects
by Chiang, Ting-Yen, Ph.D., Stanford University, 2004, 121 pages; AAT 3128364
Preview (528 K) ***  Full Text - PDF (5 MB)  
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232.
Energy aware VLSI designs for reconfigurable DSP architectures
by Chin, Shu-Shin, Ph.D., State University of New York at Stony Brook, 2004, 159 pages; AAT 3161097
Preview (577 K) ***  Full Text - PDF (7 MB)  
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233.
Frequency dependent VLSI circuit modeling and design
by Mei, Shizhong, Ph.D., Northwestern University, 2004, 134 pages; AAT 3132565
Preview (570 K) ***  Full Text - PDF (4 MB)  
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234.
High-level synthesis and rapid prototyping of asynchronous VLSI systems
by Wong, Catherine Grace, Ph.D., California Institute of Technology, 2004, 190 pages; AAT 3151405
Preview (610 K) ***  Full Text - PDF (8 MB)  
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235.
Incremental routing algorithms for FPGAs and VLSI circuits
by Arslan, Hasan, Ph.D., University of Illinois at Chicago, 2004, 153 pages; AAT 3154441
Preview (959 K) ***  Full Text - PDF (8 MB)  
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236.
Interconnect-centric circuit modeling and simulation for giga-hertz VLSI signal/power integrity applications
by Chen, Tsung-Hao, Ph.D., The University of Wisconsin - Madison, 2004, 117 pages; AAT 3127992
Preview (501 K) ***  Full Text - PDF (4 MB)  
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237.
Modeling and design techniques for improved delay, power and signal integrity in nanoscale VLSI
by Agarwal, Kanak B., Ph.D., University of Michigan, 2004, 266 pages; AAT 3150143
Preview (709 K) ***  Full Text - PDF (11 MB)  
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238.
Multilevel circuit partitioning for computer-aided VLSI design
by Cheon, Yongseok, Ph.D., The University of Texas at Austin, 2004, 135 pages; AAT 3142709
Preview (329 K) ***  Full Text - PDF (962 K)  
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239.
Multilevel VLSI placement in very deep sub-micron technology
by Hu, Bo, Ph.D., University of California, Santa Barbara, 2004, 158 pages; AAT 3136890
Preview (637 K) ***  Full Text - PDF (6 MB)  
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240.
New strategies for high performance VLSI physical design
by Xiang, Hua, Ph.D., University of Illinois at Urbana-Champaign, 2004, 168 pages; AAT 3131057
Preview (1 MB) ***  Full Text - PDF (12 MB)  
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241.
New VLSI design of a MAP/BCJR decoder
by Sabeti, Leila, M.A.Sc., University of Windsor (Canada), 2004, 120 pages; AAT MR00161
Preview (807 K) ***  Full Text - PDF (4 MB)  
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242.
Noise analysis and design methodologies in deep sub-micron VLSI circuits
by Chowdhury, M. Masud Hasan, Ph.D., Northwestern University, 2004, 196 pages; AAT 3132502
Preview (583 K) ***  Full Text - PDF (6 MB)  
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243.
Noise modeling, evaluation and noise-tolerant design of very deep submicron VLSI circuits
by Ding, Li, Ph.D., University of Michigan, 2004, 156 pages; AAT 3121921
Preview (1 MB) ***  Full Text - PDF (12 MB)  
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244.
Power distribution network analysis and optimization in digital VLSI circuits
by Bai, Geng, Ph.D., University of Illinois at Urbana-Champaign, 2004, 118 pages; AAT 3130874
Preview (703 K) ***  Full Text - PDF (4 MB)  
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245.
Real-time transient stability analysis by analog VLSI and transient stability enhancement
by Gu, Jun, Ph.D., Arizona State University, 2004, 206 pages; AAT 3123563
Preview (1 MB) ***  Full Text - PDF (13 MB)  
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246.
Routing congestion analysis and reduction in deep sub-micron VLSI design
by Shen, Zion Cien, Ph.D., Iowa State University, 2004, 132 pages; AAT 3145682
Preview (674 K) ***  Full Text - PDF (5 MB)  
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247.
Sequential/parallel global routing algorithms for VLSI standard cells
by Sun, Hao, M.Sc., University of Guelph (Canada), 2004, 129 pages; AAT MQ96212
Preview (647 K) ***  Full Text - PDF (6 MB)  
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248.
Study on reliability of VLSI interconnection structures
by Kim, Dae-Yong, Ph.D., Stanford University, 2004, 124 pages; AAT 3111736
Preview (669 K) ***  Full Text - PDF (8 MB)  
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249.
Synthesis and performance prediction of VLSI designs
by Karandikar, Shrirang K., Ph.D., University of Minnesota, 2004, 108 pages; AAT 3154053
Preview (740 K) ***  Full Text - PDF (6 MB)  
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250.
Thermal and power integrity analysis and optimization for high performance VLSI
by Wang, Ting-Yuan, Ph.D., The University of Wisconsin - Madison, 2004, 103 pages; AAT 3143222
Preview (694 K) ***  Full Text - PDF (6 MB)  
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251.
Unification of VLSI placement and floorplanning
by Adya, Saurabh N., Ph.D., University of Michigan, 2004, 159 pages; AAT 3150142
Preview (785 K) ***  Full Text - PDF (8 MB)  
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252.
VLSI layout verification using adaptive critic designs and fuzzy logic
by Zhang, Nian, Ph.D., University of Missouri - Rolla, 2004, 80 pages; AAT 3143766
Preview (754 K) ***  Full Text - PDF (5 MB)  
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253.
Adaptive analog VLSI signal processing and neural networks
by Dugger, Jeff, Ph.D., Georgia Institute of Technology, 2003, 127 pages; AAT 3117931
Preview (230 K) ***  Full Text - PDF (1 MB)  
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254.
Algorithms for VLSI design planning
by Chen, Hung-Ming, Ph.D., The University of Texas at Austin, 2003, 119 pages; AAT 3116281
Preview (222 K) ***  Full Text - PDF (636 K)  
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255.
Algorithms for VLSI physical design
by Yildiz, Mehmet Can, Ph.D., State University of New York at Binghamton, 2003, 133 pages; AAT 3102091
Preview (636 K) ***  Full Text - PDF (6 MB)  
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256.
Analysis and design of CMOS VLSI considering uncertainties in circuit parameters
by Choi, Seung Hoon, Ph.D., Purdue University, 2003, 145 pages; AAT 3122832
Preview (1 MB) ***  Full Text - PDF (10 MB)  
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257.
A new ATPG algorithm to generate compact test sets which detect static and dynamic defects in VLSI circuits
by Lee, Sooryong, Ph.D., Texas A&M University, 2003, 76 pages; AAT 3102502
Preview (450 K) ***  Full Text - PDF (3 MB)  
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258.
A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications
by Pontikakis, Bill, M.A.Sc., Concordia University (Canada), 2003, 68 pages; AAT MQ83874
Preview (353 K) ***  Full Text - PDF (2 MB)  
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259.
Area/congestion-driven placement for VLSI circuit layout
by Yang, Zhen, M.Sc., University of Guelph (Canada), 2003, 169 pages; AAT MQ85120
Preview (756 K) ***  Full Text - PDF (9 MB)  
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260.
A reconfigurable hardware implementation of genetic algorithms for VLSI CAD design
by Koonar, Gurwant Kaur, M.Sc., University of Guelph (Canada), 2003, 159 pages; AAT MQ85068
Preview (556 K) ***  Full Text - PDF (7 MB)  
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261.
A very wideband operational transconductance amplifier and capacitor (OTA-C) filter in CMOS VLSI technology
by Li, Rong Ding, M.A.Sc., Concordia University (Canada), 2003, 124 pages; AAT MQ83870
Preview (566 K) ***  Full Text - PDF (4 MB)  
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262.
A VLSI architecture for lifting-based wavelet packet transform in fingerprint image compression
by Zhu, Tao, M.S.E., University of Nevada, Las Vegas, 2003, 105 pages; AAT 1417747
Preview (720 K) ***  Full Text - PDF (4 MB)  
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263.
A VLSI sensory-motor architecture for an obstacle avoidance task in an unstructured environment
by Claveau, C. David, M.A.Sc., Concordia University (Canada), 2003, 107 pages; AAT MQ77966
Preview (612 K) ***  Full Text - PDF (4 MB)  
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264.
CAD algorithms for VLSI design and manufacturing
by Huang, Li-Da, Ph.D., The University of Texas at Austin, 2003, 126 pages; AAT 3119530
Preview (302 K) ***  Full Text - PDF (2 MB)  
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265.
Crosstalk noise management in VLSI routing
by Morton, Paul B., Ph.D., University of California, Santa Cruz, 2003, 216 pages; AAT 3080501
Preview (538 K) ***  Full Text - PDF (6 MB)  
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266.
Design and analysis of a 32 x 32-bit database filter chip based on a CMOS compatible photonic VLSI device technology
by Tang, Jianjing, Ph.D., University of Cincinnati, 2003, 113 pages; AAT 3121102
Preview (573 K) ***  Full Text - PDF (6 MB)  
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267.
Digital control of switching converters design and VLSI/DSP implementation
by Prodic', Aleksandar Milivo'je, Ph.D., University of Colorado at Boulder, 2003, 186 pages; AAT 3096842
Preview (930 K) ***  Full Text - PDF (7 MB)  
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268.
Early power estimation for VLSI circuits
by Buyuksahin, Kavel M., Ph.D., University of Illinois at Urbana-Champaign, 2003, 111 pages; AAT 3086027
Preview (649 K) ***  Full Text - PDF (4 MB)  
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269.
Energy aware VLSI architectures for mobile video applications
by Darwish, Tarek Khaled, Ph.D., University of Louisiana at Lafayette, 2003, 148 pages; AAT 3108247
Preview (640 K) ***  Full Text - PDF (6 MB)  
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270.
Enhancing defect coverage of VLSI chips by using cost effective delay fault tests
by Sharma, Manish, Ph.D., University of Illinois at Urbana-Champaign, 2003, 108 pages; AAT 3101968
Preview (615 K) ***  Full Text - PDF (4 MB)  
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271.
Genetic algorithm for VLSI physical design
by Bhattacharjee, Anirban K., M.E.S., Lamar University - Beaumont, 2003, 115 pages; AAT 1417350
Preview (1 MB) ***  Full Text - PDF (7 MB)  
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272.
High level techniques for leakage power estimation and optimization in VLSI ASICs
by Gopalakrishnan, Chandramouli, Ph.D., University of South Florida, 2003, 124 pages; AAT 3133515
Preview (236 K) ***  Full Text - PDF (1 MB)  
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273.
High throughput VLSI architectures for iterative decoders
by Yeo, Engling, Ph.D., University of California, Berkeley, 2003, 164 pages; AAT 3183880
Preview (81 K) ***  Full Text - PDF (3 MB)  
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274.
Incremental diagnosis in digital VLSI circuits
by Liu, Jiang Brandon, M.A.Sc., University of Toronto (Canada), 2003, 81 pages; AAT MQ78171
Preview (394 K) ***  Full Text - PDF (3 MB)  
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275.
Installation and development of VLSI nanotechnology computer simulation capability
by Chaganty, Rangasai Venkata, M.S., The University of Texas at El Paso, 2003, 146 pages; AAT EP10531
Preview (492 K) ***  Full Text - PDF (3 MB)  
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276.
Layout density control for improved VLSI manufacturability
by Chen, Yu, Ph.D., University of California, Los Angeles, 2003, 163 pages; AAT 3110813
Preview (857 K) ***  Full Text - PDF (10 MB)  
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277.
Low complexity, high-speed VLSI architectures for error correction decoders
by Chen, Yanni, Ph.D., University of Minnesota, 2003, 128 pages; AAT 3092732
Preview (1 MB) ***  Full Text - PDF (9 MB)  
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278.
Low power high performance VLSI design in deep-submicron CMOS processes
by Hamzaoglu, Fatih, Ph.D., University of Virginia, 2003, 122 pages; AAT 3062110
Preview (720 K) ***  Full Text - PDF (5 MB)  
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279.
Massively parallel mixed-signal VLSI kernel machines
by Genov, Roman A., Ph.D., The Johns Hopkins University, 2003, 111 pages; AAT 3068153
Preview (662 K) ***  Full Text - PDF (4 MB)  
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280.
Methods for the modeling and analysis of MIS interconnects in VLSI circuits
by Jin, Zhongfang, Ph.D., Ecole Polytechnique, Montreal (Canada), 2003, 191 pages; AAT NQ98179
Preview (953 K) ***  Full Text - PDF (8 MB)  
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281.
New methods for dynamic power estimation and optimization in VLSI circuits
by Murugavel, Ashok K., Ph.D., University of South Florida, 2003, 164 pages; AAT 3116436
Preview (989 K) ***  Full Text - PDF (10 MB)  
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282.
Receiver, transmitter, and ASIC design for optoelectronic-VLSI applications
by Venditti, Michael B., Ph.D., McGill University (Canada), 2003, 247 pages; AAT NQ88595
Preview (2 MB) ***  Full Text - PDF (30 MB)  
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283.
RF/CDMA interconnect for re-configurable VLSI systems
by Xu, Zhiwei, Ph.D., University of California, Los Angeles, 2003, 104 pages; AAT 3121161
Preview (1 MB) ***  Full Text - PDF (10 MB)  
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284.
Scheduling and partitioning VLSI circuit operating at multiple supply voltages
by Wang, Ling, Ph.D., University of Nevada, Las Vegas, 2003, 92 pages; AAT 3115899
Preview (688 K) ***  Full Text - PDF (3 MB)  
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285.
Temperature-dependent mechanical behavior of silicon dioxide, gold and gold-vanadium thin films for VLSI integrated circuits and MicroElectroMechanical systems (MEMs)
by Lin, Ming-Tzer, Ph.D., Lehigh University, 2003, 311 pages; AAT 3117163
Preview (685 K) ***  Full Text - PDF (11 MB)  
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286.
Testing signal integrity in high speed VLSI chips
by Attarha, Amir Reza, Ph.D., The University of Texas at Dallas, 2003, 154 pages; AAT 3110969
Preview (589 K) ***  Full Text - PDF (6 MB)  
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287.
The chipmap(TM): Visualizing large VLSI physical design datasets
by Solomon, Jeffrey Michael, Ph.D., Stanford University, 2003, 97 pages; AAT 3085373
Preview (607 K) ***  Full Text - PDF (5 MB)  
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288.
The VLSI implementation and evaluation of area- and energy-efficient streaming media processors
by Khailany, Brucek Kurdo, Ph.D., Stanford University, 2003, 152 pages; AAT 3090624
Preview (1 MB) ***  Full Text - PDF (13 MB)  
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289.
VLSI architectures for iterative channel decoders
by Mansour, Mohammad Monzer, Ph.D., University of Illinois at Urbana-Champaign, 2003, 215 pages; AAT 3086131
Preview (812 K) ***  Full Text - PDF (10 MB)  
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290.
VLSI implementation of a turbo encoder/decoder
by Padinjare, Sainath, M.Eng., Memorial University of Newfoundland (Canada), 2003, 133 pages; AAT MQ93047
Preview (562 K) ***  Full Text - PDF (6 MB)  
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291.
VLSI interconnect synthesis and prediction
by Liu, Bao, Ph.D., University of California, San Diego, 2003, 262 pages; AAT 3077807
Preview (802 K) ***  Full Text - PDF (11 MB)  
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292.
A biomorphic analog VLSI implementation of a mammalian motor unit
by Bragg, Julian Alexander, Ph.D., Georgia Institute of Technology, 2002, 233 pages; AAT 3061401
Preview (592 K) ***  Full Text - PDF (9 MB)  
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293.
A comparative study of ciphers and their VLSI implementation for low-power communications
by Lewis, Matthew D. T., M.Sc., Queen's University at Kingston (Canada), 2002, 112 pages; AAT MQ65633
Preview (668 K) ***  Full Text - PDF (3 MB)  
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294.
Advanced plasma etching processes for dielectric materials in VLSI technology
by Wang, Juan Juan, Ph.D., University of Florida, 2002, 156 pages; AAT 3056793
Preview (769 K) ***  Full Text - PDF (5 MB)  
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295.
Delay modeling and optimization in VLSI circuit synthesis
by Ketkar, Mahesh Chandraprakash, Ph.D., University of Minnesota, 2002, 90 pages; AAT 3058649
Preview (513 K) ***  Full Text - PDF (3 MB)  
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296.
Design and analysis of compensated operational amplifier using VLSI CAD tools
by Nethi, Murali Krishna, M.S., University of Louisville, 2002, 51 pages; AAT 1409325
Preview (198 K) ***  Full Text - PDF (1 MB)  
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297.
Design and optimization of global interconnect in high speed VLSI circuits
by Su, Haihua, Ph.D., University of Minnesota, 2002, 114 pages; AAT 3034461
Preview (471 K) ***  Full Text - PDF (4 MB)  
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298.
Design methodology for analog VLSI implementations of error control decoders
by Dai, Jie, Ph.D., The University of Utah, 2002, 207 pages; AAT 3067623
Preview (664 K) ***  Full Text - PDF (7 MB)  
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299.
Design of high-performance VLSI RLC interconnects
by Awwad, Falah Rashad, M.A.Sc., Concordia University (Canada), 2002, 69 pages; AAT MQ68437
Preview (336 K) ***  Full Text - PDF (2 MB)  
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300.
Efficient VLSI architectures for error-correcting coding
by Zhang, Tong, Ph.D., University of Minnesota, 2002, 166 pages; AAT 3059921
Preview (515 K) ***  Full Text - PDF (5 MB) 
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